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71M6533/G/H and 71M6534/H Data Sheet
FDS_6533_6534_004
If the MPU overwrites the CE’s working RAM, the CE’s output may be corrupted. If the CE is
disabled, the first 0x40 bytes of RAM are still unusable while MUX_DIV[3:0] ≠ 0 because the
71M6533/71M6534 ADC writes to these locations. Setting MUX_DIV[3:0] = 0 disables the ADC
output, preventing the CE from writing the first 0x40 bytes of RAM.
The 80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX
@DPTR,A instruction. The MPU reads external data memory by executing a MOVX A,@Ri or MOVX
A,@DPTR instruction (SFR PDATA provides the upper 8 bytes for the MOVX A,@Ri instruction).
Internal and External Memory Map
Table 7 shows the address, type, use and size of the various memory components.
Only the memory ranges shown in Table 7 contain physical memory.
Table 7: Memory Map
Address
(hex)
00000-1FFFF
00000-3FFFF ?
on 1K
boundary
0000-0FFF
2000-20BF,
20C8-20FF
20C0-20C7
0000-00FF
Memory
Technology
Flash Memory
Flash Memory
Flash Memory
Static RAM
Static RAM
Static RAM
Static RAM
Memory
Type
Non-
volatile
Non-
volatile
Non-
volatile
Volatile
Volatile
Non-
volatile
(battery)
Volatile
Name
Program memory
Program memory
Program memory
External RAM
(XRAM)
Configuration RAM
(I/O RAM)
Configuration RAM
(I/O RAM)
Internal RAM
Typical Usage
MPU Program and
non-volatile data
MPU Program and
non-volatile data
CE program
Shared by CE and
MPU
Hardware control
Battery-buffered
memory
Part of 80515 Core
Memory Size
(bytes)
128 KB
256 KB ?
8 KB max.
4 KB
256
8
256
?
For the 71M6534 only.
MOVX Addressing
There are two types of instructions differing in whether they provide an 8-bit or 16-bit indirect address to
the external data RAM.
In the first type, MOVX A,@Ri, the contents of R0 or R1 in the current register bank provide the eight
lower-ordered bits of address. The eight high-ordered bits of the address are specified with the PDATA
SFR. This method allows the user paged access (256 pages of 256 bytes each) to all ranges of the
external data RAM.
In the second type of MOVX instruction, MOVX A,@DPTR, the data pointer generates a 16-bit address.
This form is faster and more efficient when accessing very large data arrays (up to 64 KB), since no
additional instructions are needed to set up the eight high ordered bits of the address.
It is possible to mix the two MOVX types. This provides the user with four separate data pointers, two
with direct access and two with paged access, to the entire 64 KB of external memory range.
Dual Data Pointer
The Dual Data Pointer accelerates the block moves of data. The standard DPTR is a 16-bit register that
is used to address external memory or peripherals. In the 80515 core, the standard data pointer is called
DPTR , the second data pointer is called DPTR1 . The data pointer select bit, located in the LSB of the DPS
register ( DPS [0]), chooses the active pointer. DPTR is selected when DPS[0] = 0 and DPTR1 is selected
when DPS[0] = 1.
20
Rev 2
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71M6533H-IGT/F1 功能描述:计量片上系统 - SoC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 处理器系列:71M6511 类型:Metering SoC 最大时钟频率:70 Hz 程序存储器大小:64 KB 数据 RAM 大小:7 KB 接口类型:UART 可编程输入/输出端数量:12 片上 ADC: 安装风格:SMD/SMT 封装 / 箱体:LQFP-64 封装:Reel
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